1. Field of the Invention
The present invention relates in general to a comparator. More specifically, it relates to a comparator utilizing a plurality of inverters, connected in series, and a plurality of switches to enhance its operation speed.
2. Description of the Related Art
At present, most electronic systems use powerful microprocessors to process digitized data. Analog-to-digital converters, ADC hereinafter, serve a critical role in digitalization as interface media between analog signals and digital signals.
In general, either parallel-connected converters or flash converters are utilized to implement ADC converters, both of which output binary codes from an encoder after an analog signal is sampled and its voltage level compared with several reference voltage levels. An outputted binary code corresponds to the reference voltage level closest to the voltage level of the analog signal.
A flash ADC usually requires a large number of comparators for implementation. In order to simplify the design of the ADC in high-resolution applications, an ADC using a plurality of transforming stages for reducing the number of comparators has been proposed. For example, two-step analog-to-digital converters are commonly used for transforming analog input voltage into a digital code. The two-step ADC will first roughly determine the voltage range closest to the input voltage, thereby obtaining a high-bit portion (MSB) of the digital code. The two-step ADC will then further subdivide the closest voltage range determined above and compare the input voltage therein, thereby obtaining a low-bit portion (LSB) of the digital code.
In general, a two-step ADC uses comparators of the inverter type for obtaining both the high-bit portion (MSB) of the digital code and the low-bit portion (LSB) of the digital code. However, the signal (or voltage level) used for comparing to obtain the low-bit portion (LSB) of the digital code is usually small, and therefore the output voltage of the comparator requires a longer time to reach its steady state, thus resulting in a reduction and limitation of the converting speed of the ADC. When the resolution of an ADC is enhanced, the signal used for obtaining the low-bit portion (LSB) of the digital code becomes even smaller, thereby even further reducing the converting speed of the ADC.
FIG. 1A and FIG. 1B illustrate the structure of a conventional comparator and the timing chart of its operation, respectively. In FIG. 1A, two input terminals of two select switches (CKvin and CKvref) are coupled to an input voltage Vin and a reference voltage Vref, and both output terminals are coupled to one terminal of a capacitor C1; two inverters A1 and A2 are connected with two switches az1 and az2 in parallel, respectively, and the other terminal of the capacitor C1 is coupled to the input terminal of the inverter A1; a capacitor C2 is provided between the output terminal of the inverter A1 and the input terminal of the inverter A2; and the output terminal of the inverter A2 is coupled to the input terminal of the inverter A3. The operation of the comparator depicted in FIG. 1 will be described as follows in accompaniment with FIG. 1B, FIG. 2A, and FIG. 2B.
In time interval (1), since the switches az1, az2, and the select switch CKvin are turned on, and the select switch CKvref is turned off, the circuit topology of the comparator is depicted as FIG. 2A. The voltage levels at P1.about.P4 are the threshold voltage Vth of the inverters, because the input and output terminals of the inverters (A1 and A2) are connected together. The voltage level at P0 is Vin, and therefore the voltages stored in capacitors C1 and C2 are (Vth-Vin) and 0, respectively. The comparator carries out the operation to take samples of the input voltage Vin.
In time interval (2), since only the select switch CKvref is turned on, and the switches az1, az2, and the select switch CKvin are turned off, the circuit topology of the comparator is depicted as FIG. 2B. The voltage at P0 is Vref and the capacitor C1 stores the voltage of (Vth-Vin), and thus the voltage at P1 becomes Vth-(Vin-Vref). The voltage at P1 is amplified by the inverter A1 and outputted to P2. The voltage at P2 can be represented as Vth+(Vin-Vref).times.M, wherein M is the gain of the inverters. The voltage stored in capacitor C2 is 0, and thus the voltage at P3 is equal to that at P2. The voltage at P3 is amplified by the inverter A2, and the voltage at P4 can be represented as Vth-(Vin-Vref).times.M.sup.2. Finally, the inverter A3 amplifies the voltage at P4 and outputs the comparing result Vout which equals Vth+(Vin-Vref) .times.M.sup.3. From above descriptions, when the comparing signal (Vin-Vref) is small, a longer time is required for reaching an output of steady state during the amplifying operation of every inverter, thereby limiting the operating speed of the comparator.